Projects

Here are some projects and areas I’ve worked on. Each card links to more context or the project itself.

Protago AI — Personalised Storybook Pipeline

Protago AI — Personalised Storybook Pipeline

Built an end-to-end storybook generation product: text-to-image via Flux diffusion models with LoRA fine-tuning on Modal, combined with a BFS face-swap pipeline to personalise characters to the child's likeness. Deployed to production with a real-time preview experience. Drove ₹50k+ revenue in two months through Instagram content strategy, influencer collabs, and targeted ads.

Flux LoRA Diffusion Models Modal Face Swap Production AI
iCurious AI — Voice AI Companion for Kids

iCurious AI — Voice AI Companion for Kids

Architected a real-time voice AI pipeline (STT + LLM inference + TTS) for a hardware AI companion, deployed on both edge hardware and cloud backends. Designed a persistent memory architecture storing child-specific context across sessions, and a Socratic questioning pipeline that guides children toward answers rather than giving them directly. Led hardware prototyping lifecycle including 3D-printed enclosures and alpha testing. Secured 12L+ in NIDHI Prayas and MeitY government grants.

Voice AI Edge AI Memory Systems LLM TTS Hardware Prototyping
HIWE — Scene Importance Weighted Encoding for NeRF

HIWE — Scene Importance Weighted Encoding for NeRF

Research at the University of Toronto. Identified that uniform parameter allocation in grid-based NeRF encodings (like iNGP) fails on large outdoor scenes. Proposed HIWE: a novel positional encoding that adaptively allocates more model capacity to high-importance scene regions, improving reconstruction quality without increasing total model size.

NeRF Computer Vision PyTorch Scene Representation Research
NICraft — Malicious NIC Firmware Cache Side-Channel

NICraft — Malicious NIC Firmware Cache Side-Channel

Security research at CISPA Helmholtz Center. Uncovered a Prime+Probe gadget in the Linux kernel's TCP/IP stack IP reassembly path, enabling a cache side-channel triggered entirely by incoming network packets. Demonstrated a malicious NIC firmware attack achieving 96%+ precision in detecting keystroke activity across 20 users — with zero user-space access. Published at ESORICS 2025.

Systems Security Cache Side-Channels Linux Kernel Microarchitecture ESORICS 2025
Databricks Observability Platform

Databricks Observability Platform

Built core infrastructure for Databricks' internal observability platform. Drove $5M annual savings by attributing and eliminating high-cost metric emission sources. Improved HMR reliability from 90% to 99%. Designed Grafana query attribution as the foundational layer for intelligent per-team cost accountability.

Observability Grafana Infrastructure Cost Engineering Distributed Systems

Bitcoin Core — ComplexMempool Benchmark Fix

Fixed a correctness bug in Bitcoin Core's ComplexMempool benchmark: ancestor and descendant tracking in the mempool graph algorithms was incorrect, producing misleading benchmark results. PR #22856 merged into bitcoin/bitcoin, December 2021.

Bitcoin C++ Open Source Graph Algorithms

MIPS Processor Simulator + Branch Predictors

Built a fully pipelined MIPS processor simulator with five pipeline stages, interlock cycle detection, and data forwarding paths. Implemented and benchmarked bimodal, gshare, and tournament branch predictors alongside LRU, RRIP, and Hawkeye cache replacement policies; evaluated on SPEC CPU benchmarks.

Computer Architecture C++ Simulation Microarchitecture

Java → x86 Compiler

Built a complete compiler from scratch for a subset of Java targeting Intel x86 (32-bit) assembly. Used Flex and Bison for lexing and parsing, with a hand-crafted symbol table and AST. Implemented semantic analysis, three-address IR generation, and x86 code emission with OOP features, recursion, and method overloading.

Compilers x86 Flex Bison Systems